A 30mV input battery-less power management system

This paper presents a fully-integrated on chip battery-less power management system through energy harvesting circuit developed in a 130nm CMOS process. A 30mV input voltage from a TEG is able to be boosted by the proposed Complementary Metal-Oxide-Semiconductor (CMOS) voltage booster and a dynamic closed loop power management to a regulated 1.2V. Waste body heat is harvested through Thermoelectric energy harvesting to power up low power devices such as Wireless Body Area Network. A significant finding where 1 Degree Celsius thermal difference produces a minimum 30mV is able to be boosted to 1.2V. Discontinuous Conduction Mode (DCM) digital control oscillator is the key component for the gate control of the proposed voltage booster. Radio Frequency (RF) rectifier is utilized to act as a start-up mechanism for voltage booster and power up the low voltage closed loop power management circuit. The digitally control oscillator and comparator are able to operate at low voltage 600mV which are powered up by a RF rectifier, and thus to kick-start the voltage booster

128 mA CMOS LDO with 108 db PSRR at 2.4 MHz frequency

A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1µF off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC. The characteristic is achieved by implementing MOSFET transistors operate in weak and strong inversions. The LDO is designed using 0.18µm CMOS technology and achieves a constant 1.8V output voltage for input voltages from 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The proposed LDO is targeted for RF application which has stringent requirement on noise rejection over a broad range of frequency

Impedance matching and DC-DC converter designs for tunable radio frequency based mobile telecommunication systems

Tunability and adaptability for radio frequency (RF) front-ends are highly desirable because they not only enhance functionality and performance but also reduce the circuit size and cost. This thesis presents a number of novel design strategies in DC-DC converters, impedance networks and adaptive algorithms for tunable and adaptable RF based mobile telecommunication systems. Specifically, the studies are divided into three major directions: (a) high voltage switch controller based DC-DC converters for RF switch actuation; (b) impedance network designs for impedance transformation of RF switches; and (c) adaptive algorithms for determining the required impedance states at the RF switches. In the first stage, two-phase step-up switched-capacitor (SC) DC-DC converters are explored. The SC converter has a simple control method and a reduced physical volume. The research investigations started with the linear and the non-linear voltage gain topologies. The non-linear voltage gain topology provides a higher voltage gain in a smaller number of stages compared to the linear voltage gain topology. Amongst the non-linear voltage gain topologies, a Fibonacci SC converter has been identified as having lower losses and a higher conversion ratio compared to other topologies. However, the implementation of a high voltage (HV) gain Fibonacci SC converter is complex due to the requirement of widely different gate voltages for the transistors in the Fibonacci converter. Gate driving strategies have been proposed that only require a few auxiliary transistors in order to provide the required boosted voltages for switching the transistors on and off. This technique reduces the design complexity and increases the reliability of the HV Fibonacci SC converter. For the linear voltage gain topology, a high performance complementary-metaloxide- semiconductor (CMOS) based SC DC-DC converter has been proposed in this work. The HV SC DC-DC converter has been designed in low voltage (LV) transistors technology in order to achieve higher voltage gain. Adaptive biasing circuits have been proposed to eliminate the leakage current, hence avoiding latch-up which normally occurs with low voltage transistors when they are used in a high voltage design. Thus, the SC DC-DC converter achieves more than 25% higher boosted voltage compared to converters that use HV transistors. The proposed design provides a 40% power reduction through the charge recycling circuit that reduces the effect of non-ideality in integrated HV capacitors. Moreover, the SC DC-DC converter achieves a 45% smaller area than the conventional converter through optimising the design parameters. In the second stage, the impedance network designs for transforming the impedance of RF switches to the maximum achievable impedance tuning region are investigated. The maximum achievable tuning region is bounded by the fundamental properties of the selected impedance network topology and by the tunable values of the RF switches that are variable over a limited range. A novel design technique has been proposed in order to achieve the maximum impedance tuning region, through identifying the optimum electrical distance between the RF switches at the impedance network. By varying the electrical distance between the RF switches, high impedance tuning regions are achieved across multi frequency standards. This technique reduces the cost and the insertion loss of an impedance network as the required number of RF switches is reduced. The prototype demonstrates high impedance coverages at LTE (700MHz), GSM (900MHz) and GPS (1575MHz). Integration of a tunable impedance network with an antenna for frequency-agility at the RF front-end has also been discussed in this work. The integrated system enlarges the bandwidth of a patch antenna by four times the original bandwidth and also improves the antenna return loss. The prototype achieves frequency-agility from 700MHz to 3GHz. This work demonstrates that a single transceiver with multi frequency standards can be realised by using a tunable impedance network. In the final stage, improvement to an adaptive algorithm for determining the impedance states at the RF switches has been proposed. The work has resulted in one more novel design techniques which reduce the search time in the algorithm, thus minimising the risk of data loss during the impedance tuning process. The approach reduces the search time by more than an order of magnitude by exploiting the relationships among the mass spring’s coefficient values derived from the impedance network parameters, thereby significantly reducing the convergence time of the algorithm. The algorithm with the proposed technique converges in less than half of the computational time compared to the conventional approach, hence significantly improving the search time of the algorithm. The design strategies proposed in this work contribute towards the realisation of tunable and adaptable RF based mobile telecommunication systems

3.3V DC Output At-16dBm Sensitivity And 77% PCE Rectifier For RF Energy Harvesting

This paper presents a high voltage conversion at high sensitivity RF energy harvesting system for IoT applications. The harvesting system comprises bulk-to-source (BTMOS) differential-drive based rectifier to produce a high efficiency RF energy harvesting system. Low-pass upward impedance matching network is applied at the rectifier input to increase the sensitivity and output voltage. Dual-oxide-thickness transistors are used in the rectifier circuit to maintain the power efficiency at each stage of the rectifier. The system is designed using 0.18μm Silterra RF in deep n-well process technology and achieves 4.07V output at -16dBm sensitivity without the need of complex auxiliary control circuit and DC-DC charge-pump circuit. The system is targeted for urban environment

Design consideration in low dropout voltage regulator for batteryless power management unit

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology

Neuromorphic solutions: Digital implementation of bio-inspired spiking neural network for electrocardiogram classification

Conventional techniques of off-chip processing for wearable devices cause high hardware resource usage which leads to heat generation and increased power consumption. Hence, edge computing methods such as neuromorphic computing are considered the most promising modern technology to replace conventional processing. It is beneficial to employ neuromorphic processing in electrocardiogram (ECG) classification, enabling engineers to overcome the constraints of heat generation caused by hardware utilization. Thus, this work aims to investigate common building blocks in a spiking neural network (SNN), analyze the spike-based plasticity mechanism and implement ECG classification on a neuromorphic circuit. The MIT-BIH Arrhythmia database (MITDB) is preprocessed in MATLAB, then used to train and test an SNN designed for field programmable gate arrays (FPGA), employing spike-based plasticity and Izhikevich neurons. The behaviour of spike timing dependent plasticity (STDP) in a neuromorphic circuit is also visualized in this work. The state-of the-art performance of this work lies in providing a generic mechanism to adapt ECG classification into a neuromorphic solution, a non-Von Neumann architecture. The proposed digital design utilizes 1.058% of hardware resources on a Zedboard. Application-wise, this work provides a foundation for development of neuromorphic computing in wearable medical devices that perform continuous monitoring of ECG

A 30mV Input Battery-Less Power Management System

This paper presents a fully-integrated on chip battery-less power management system through energy harvesting circuit developed in a 130nm CMOS process. A 30mV input voltage from a TEG is able to be boosted by the proposed Complementary Metal-Oxide-Semiconductor (CMOS) voltage booster and a dynamic closed loop power management to a regulated 1.2V. Waste body heat is harvested through Thermoelectric energy harvesting to power up low power devices such as Wireless Body Area Network. A significant finding where 1 Degree Celsius thermal difference produces a minimum 30mV is able to be boosted to 1.2V. Discontinuous Conduction Mode (DCM) digital control oscillator is the key component for the gate control of the proposed voltage booster. Radio Frequency (RF) rectifier is utilized to act as a start-up mechanism for voltage booster and power up the low voltage closed loop power management circuit. The digitally control oscillator and comparator are able to operate at low voltage 600mV which are powered up by a RF rectifier, and thus to kick-start the voltage booste

Neuromorphic computing based on stochastic spiking reservoir for heartbeat classification

Heart disease is the leading cause of mortality worldwide. The precise heartbeat classification usually requires a higher number of extracted features and heartbeats of the same class may also behave differently in patients. This will lead to computation overhead and challenges in hardware implementation due to the large number of nodes utilized in reservoir computing (RC) networks. In this work, a reservoir computing-based stochastic spiking neural network (SSNN) has been proposed for heartbeat rhythm classification, enabling a patient adaptable and more efficient hardware implementation with low computation overhead caused by minimum extracted features. Only a single feature is employed in template matching to achieve patient adaptability with minimal computation overhead. The single feature, QRS complexes, was extracted and fed into the neural reservoir with 20 neurons in a cyclic topology for arrhythmia similarity calculation and classification. 43 recordings of Electrocardiogram (ECG) signals that included both normal and arrhythmic beats from MIT-BIH arrhythmia database obtained from Physio-Net were used in this work. The proposed stochastic spiking reservoir achieves a sensitivity of 99.6% and an accuracy of 96.91%, signifying that the system is accurate and efficient in classifying normal and abnormal arrhythmias